1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory having a test mode signal generating circuit for setting a test mode.
2. Prior Art
As a result of continuous development, the capacity of semiconductor memories has steadily increased. However, the greater the memory capacity, the longer the test time. To overcome this drawback, a DRAM having a memory capacity of 1M bits or more has been developed which incorporates a parallel test function in order to reduce the test time.
FIG. 1 shows an example of a test mode signal generating circuit for a test mode entry (test mode setting).
The test mode signal generating circuit includes a first test mode signal generating circuit 1, a second test mode signal generating circuit 2b, and a reset signal generating circuit 5. The first test mode signal generating circuit 1 is provided with a logic gate G1, an inverter IV1, and a flip-flop FF1.
An operation of the test mode signal generating circuit shown in FIG. 1 will now be described, with reference to FIGS. 2A through 2F.
The inverter IV1 inverts a row address strobe signal RASb (active low) shown in FIG. 2A and supplies it to clock input terminals of flip-flops FF1 and FF2. A gate G1 supplies a high level signal to a D-input terminal of the first flip-flop FF1 when a column address strobe signal CASb (active low) shown in FIG. 2B and a write enable signal WEb (active low) shown in FIG. 2C are both at low level.
If the column address strobe signal CASb shown in FIG. 2B and the write enable signal WEb shown in FIG. 2C are both at low level when the row address strobe signal RASb changes from high level to low level, the flip-flop FF1 sets a first test mode signal TSTa shown in FIG. 2E at high level (active high) indicating a test mode.
When a one-bit (Aj) input terminal TAj of an address signal receives a voltage (a voltage higher than a power supply voltage Vcc, for example) higher than a normal operation voltage as shown in FIG. 2E, a voltage detecting circuit 22 supplies a high-level signal VD to a D-input terminal of the second flip-flop FF2. Accordingly, when the row address strobe signal RASb changes from high level to low level and when a high voltage is applied to the input terminal TAj, the second flip-flop FF2 latches a high-level signal and sets its Q output at a high level.
A gate G2 generates an active (high level) test mode signal TSTb shown in FIG. 2F, when the Q output of the flip-flop FF2 and the first test mode signal TSTa are both at high level.
A reset signal generating circuit 5 generates a reset signal RST when the row address strobe signal RASb and the column address strobe signal CASb satisfy a predetermined level relation, i.e., when both signals are at high level. The flip-flops FF1 and FF2 are reset by the reset signal RST, and the first and second test mode signals TSTa and TSTb assume an inactive level.
A timing for generating the first test mode signal TSTa is opened to a public, or users, as JFDEC standard. More specifically, the timing is determined by WCBR (write CAS before RAS). Accordingly, a user can arbitrarily set the test circuit in the test mode by using the first test mode signal to test the semiconductor memory.
A second test mode is not available to a user, but is reserved by the manufacturer and used to check an operation and the like of the semiconductor memory before shipping.
The high-voltage detecting circuit 22 is provided with cascade-connected diodes D1 through Dm, a transistor Q1, and inverters IV4a and IV5, as shown in FIG. 3, for example. Let it now be assumed that a threshold voltage of the inverter IV4 is V1 and a forward voltage of each of the diodes D1 through Dm is V2. When a voltage higher than (V1+m.multidot.V2) is applied to the input terminal TAj, an output signal VD of the inverter IV5 assumes a high level. Assuming that m=7, V1=3 V, and V2=1 V, then the voltage to be applied to the input terminal TAj is higher than 10 V.
As described above, in a conventional semiconductor memory, a voltage higher than a normal operation voltage is applied to the input terminal TAj to thereby make the second test mode signal TSTb active. A level detected by the high-voltage detecting circuit 22 changes as a result of a change in the threshold level and the like, due to variations in the process of manufacturing the transistor Q1, and the diodes D1 through Dm and the inverter IV4. For this reason, there is a possibility that the second test mode signal TSTb cannot be reliably set at the active level.
If the voltage to be applied to the input terminal TAj is increased in order to overcome this problem, it is possible that an excessively high voltage may be applied to the circuit elements connected to the input terminal TAj, thereby resulting reducing the in reliability of the memory device.